The present application relates to light-emitting diodes and manufacturing methods thereof. The present application is particularly suitable for application in microscopic light-emitting diodes.
There have been proposed microscopic light-emitting diodes that measure about several ten micrometers (see, for example, WO 2002/07231, and JP-A-2005-150673). An example of such light-emitting diodes is a light-emitting diode that uses a compound semiconductor, such as an AlGaInP semiconductor, having a zincblende crystal structure.
An example of a manufacturing method of such a light-emitting diode is described below with reference to FIG. 14A to 14C. According to this manufacturing method, as illustrated in FIG. 14A, a semiconductor layer 102 to form a light-emitting diode structure is first grown on a GaAs substrate 101 whose principal surface lies on the (001) plane. The semiconductor layer 102 is of a compound semiconductor having a zincblende crystal structure. The semiconductor layer 102 includes an active layer 102a, and additional layers such as an n-type clad layer and a p-type clad layer. Then, as illustrated in FIG. 14B, a resist pattern 103 having a rectangular planar shape is formed on the semiconductor layer 102. The planar shape of the resist pattern 103 is shown in FIG. 15. As illustrated in FIG. 15, the resist pattern 103 has a longer side that extends in the [−110] or [1-10] direction of the semiconductor layer 102, and a shorter side that extends in the [110] or [−1-10] direction of the semiconductor layer 102. The semiconductor layer 102 is then patterned by wet etching using the resist pattern 103. In the wet etching of the semiconductor layer 102 having a zincblende crystal structure, the semiconductor layer 102 is etched in a shape according to the plane direction, because the etching rate varies depending on the plane direction. Specifically, the etching rate for the {111} planes is about 1/100 of that for the {110} planes. Thus, the etching state of the semiconductor layer 102 on the longer side of the resist pattern 103 extending in the [−110] or [1-10] direction is specified by the etching rate of the {111} planes, and as such the semiconductor layer 102 is etched to have a cross sectional shape of a forward mesa configuration. The etching therefore proceeds to form {111} planes (more specifically, (111) and (−1-11) planes) in portions of the semiconductor layer 102 on the longer side of the resist pattern 103. At the completion of the etching, as illustrated in FIG. 14C, the side faces of the semiconductor layer 102 that extend in the [−110] or [1-10] direction are tilted on planes that lie on the forward mesa planes. The wet etching results in element isolation. Then, the resist pattern 103 is removed, and an electrode, either a p-side electrode or an n-side electrode, is formed on the upper surface of the semiconductor layer 102. After removing the GaAs substrate 101, an electrode of the opposite polarity, either a p-side electrode or an n-side electrode, is formed on the exposed lower surface of the semiconductor layer 102. The light-emitting diode of interest is manufactured in this manner, as illustrated in FIG. 16.
As illustrated in FIG. 16, the cross sectional shape of the semiconductor layer 102 is bilaterally symmetrical, and the angles made by side faces 102b with respect to the principal surface of the semiconductor layer 102 are about 54.7°. In this case, the light that emerges from the active layer 102a is efficiently reflected off the side faces 102b of the semiconductor layer 102 into the lower surface (light extracting face) of the semiconductor layer 102. This enables the light to be extracted with improved efficiency. FIG. 17 illustrates the measurement result of the light radiation distribution of the light-emitting diode. It can be seen from FIG. 17 that the light radiation distribution is bilaterally symmetrical.
A method is known in which a semiconductor layer to form a light-emitting diode structure is grown on a GaAs substrate whose principal surface is tilted by a predetermined angle in the [110] direction with respect to the (001) plane. This method is commonly used for the growth of a semiconductor layer 102 of a ternary or quaternary compound semiconductor having a zincblende crystal structure. According to this method, as illustrated in FIG. 18A, a light-emitting diode structure-forming semiconductor layer 202 is first grown on a GaAs substrate 201 whose principal surface is tilted by a predetermined angle in the [110] direction with respect to the (001) plane. The semiconductor layer 202 includes an active layer 202a, and additional layers such as an n-type clad layer and a p-type clad layer. Then, as illustrated in FIG. 18B, a resist pattern 203 having a rectangular planar shape is formed on the semiconductor layer 202. The planar shape of the resist pattern 203 is the same as that shown in FIG. 15. Next, as illustrated in FIG. 18C, the semiconductor layer 202 is patterned by wet etching using the resist pattern 203. The resist pattern 203 is then removed, and an electrode, either a p-side electrode or an n-side electrode, is formed on the upper surface of the semiconductor layer 202. After removing the GaAs substrate 201, an electrode of the opposite polarity, either a p-side electrode or an n-side electrode, is formed on the exposed lower surface of the semiconductor layer 202. The light-emitting diode of interest is manufactured in this manner, as illustrated in FIG. 19.